In the course of manufacturing an integrated circuit, many layers of different materials get laid down. With few exceptions each of these layers is patterned and etched into various shapes, generally lines or holes. Each time that a fresh layer is deposited and patterned the result is the creation of an uneven surface. Although well-known planarization techniques exist for smoothing out the surface, it is not practical to planarize the surface with every new layer because poor topography can result in local areas as a consequence of multilevel metallization processes.
Thus, it is not unusual for the surface of an incomplete circuit to contain a number of steps. This is illustrated schematically in FIG. 1a which shows a number of different layers such as polysilicon 1, silicon dioxide 2, and silicon nitride 4, with a layer of metal 3 covering the topmost surface. If, now, photolithography is to be performed a layer of photoresist 15 is deposited over the entire surface by a process such as spin coating. The top surface of the photoresist layer is planar as seen in FIG. 1b. The result is that the thickness of the photoresist layer various in different parts of the surface. In particular, the difference between the maximum photoresist thickness H1 and the minimum thickness H2 can be quite substantial. It is often the case that H2 is insufficient for proper exposure of the resist to be possible at that location.
It is the purpose of the present invention to determine if such thinner-than-average photoresist layers are present and if they pose a problem. In this way the effectiveness of the photoresist can be monitored at all stages of the IC manufacturing process. Note that a simple inspection of the circuit will generally not be adequate since it is not always easy to predict just where such regions of less than adequate thickness may occur. If it should turn out that somewhere in the circuit the thickness of the photoresist is insufficient, the process can be scrapped then and there, rather than at a later stage, thereby saving unnecessary process steps.
In the course of searching for prior art no references that teach the method or structure of the present invention were encountered. The following were however found to be of interest. Carney (U.S. Pat. No. 4,652,333 March 1987) describes an in-situ etch process monitor but it is quite unlike that of the present invention, being aimed at the etching of hour glass shaped lines in silicon as part of the fabrication of buried heterostructures. Leung (U.S. Pat. No. 4,717,445 January 1988) describes an etch bias monitoring technique. The approach is to include a material known to be impervious to the etchant being used and to then compare its dimensions, after etching, with those of a photoresist pattern that was etched at the same time.